Mentor Graphics Essay

Published: 2021-06-29 02:07:57
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To complete all aspects of the exercise regarding D type flip-flop, TTL and CMOS and to familiarize us with the HDL software which is Mentor Graphics Essay.
This software is capable of constructing and simulating a particular design. As for this assignment 1, we are given 4 weeks to complete the assignment. It is compulsory to attend every lab sessions as there is no alternative software to use. Only a certain limit of time is given for the use of the software and therefore designing of circuit is required to be completed before attending the lab.
To give students a first-hand understanding of the EDA lab and most importantly Mentor Graphics, a powerful tool in HDL technology. This assignment allows the students to understand or rather familiarize themselves with the design flow of the EDA software and to fully explore what the software is capable and powerful to do. Lastly, to prepare the students for the next assignments which uses the similar software. Introduction – D(elay) Flip-Flop (What You Have to Know First!)The D flip-flop is useful when a single data bit (1 or 0) is to be stored. An additional inverter to the S-R flip-flop at the R input creates a D flip-flop. The D flip-flop shown below is a modification of the clocked SR flip-flop.
The D input goes directly into the S input and the complement of the D input goes to the R input. If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and stores a 1. If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and stores a 0. The truth table below summarizes the operations of the positive edge-triggered D flip-flop. As before, the negative edge-triggered flip-flop works the same except that the falling edge of the clock pulse is the triggering edge.
InputsD CP(CLK)OutputsQ Q’Comments1 1 0SET (stores 1)0 0 1RESET (stores a 0)The circuit of a D Type flip-flop has already been given to us. We are required to construct the given circuit using Design Architect ( DA). The constructed circuit is shown in figure 1 printed out using the lab printer. Next, a symbol of the circuit is created using DA from the menu Miscellaneous followed by Generate Symbol. The created symbol is than modified. The modified symbol is shown in figure 2.
Next, Quicksim is activated mainly to invoke forces on the constructed circuit and to Trace as well as to analyze the output of the circuit through waveforms. The saved file of the constructed circuit using DA is opened in Quicksim. Firstly, the function TRACE is used to trace PRE, CLR, CLK, D, Q, QB. After this a Trace box will appear at bottom lower left of the screen. This is where the simulated waveforms will apprear.
Forces is then added to each of the traced components except for Q and QB. After forcing the components with the required values, type RUN 800. The waveforms will appear exactly the same as the required waveforms printed out in figure 3. (please note that the traced components are included in the waveform results)As we can see clearly in figure 3, the inputs of D are copied straight to the output Q.
Transitions occurs at every positive-edge of the clock. Therefore the waveforms agree with the specification mentioned above. Next, an experiment is done by changing the PRE and CLR to low. Theoretically, an illegal output would happen.
The traced output with the above configuration is printed in figure 4. We can see that when both PRE and CLR are low resulting the output of Q and QB to be high. QB is defined to be the opposite of Q. However this happens ( both are High) due to the fact that both PRE and CLR are set to low.
Therefore it is said that the output gives an illegal operation. This is because PRE and CLK cannot be set to low at the same time. PRE has to be HIGH to give an output. The next operation done to the D flip-flop is to analyze the output when the CLK and input D changes simultaneously. We do this by adding force to the CLK and .

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